Redwood is the accelerator Architect Labs unveiled on 2026-08-27: from a high-level specification written by two human architects, an AI system generated its performance model, RTL, UVM verification environments, formal proofs, firmware, drivers and compute kernels, closed every block at 95% code and functional coverage in under two weeks, and took its first RTL drop to an AMD Versal FPGA with zero bugs (company site). It lives today on the FPGA; the silicon figures — a projected Redwood Nano on Samsung 8 nm serving Qwen3 at 49 tokens per second against a Jetson Orin Nano’s measured 28, at 1.3 W against 2.6 W — are projections calibrated from FPGA measurements. In this corpus it is the product of the first-of-authorship result and the substrate on which the loop reaches silicon: Qwen3 running on it found optimizations for its own operations.
Hardware
Redwood
Architect Labs' AI inference accelerator, the first designed, verified and deployed end-to-end by an AI system from a two-person specification, running today on an AMD Versal FPGA.
Sources
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- The First AI Chip Designed End-to-End by AI (theinnermostloop.substack.com)
Development timeline
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