A model running on the chip finds optimizations for its own operations

Once Redwood was serving Qwen3 inference on its FPGA, Architect Labs exposed the model as an endpoint inside the same AI system that had generated the chip’s RTL, verification and kernels, and the model returned timing and kernel optimizations for its own operations (company site). The newsletter reads this against I. J. Good’s 1965 intelligence explosion — a machine designing better machines — noting that Good was thinking of software and that the loop now reaches silicon. It is the hardware endpoint of a kernel storyline that runs from a model topping KernelBench for the GPU kernels it runs on through kernels rewritten behind an 80% price cut and a 232-fold kernel speedup, and it follows the same issue’s first-of-authorship result; the daily issue two days later records the announcement. The figures are company-reported, the silicon numbers are FPGA-calibrated projections, and the author discloses that he advises the company.