Design Conductor started from a 219-word requirements document and, in 12 unattended hours, produced several micro-architecture variants of a complete RISC-V core (VerCore) meeting timing at 1.48 GHz on the ASAP7 PDK, with a CoreMark of 3261, roughly a 2011 Celeron, and a verified, tape-out-ready GDSII layout (arXiv). Verkor calls it the first time an autonomous agent has built a complete working CPU from spec to layout. In the recursive-self-improvement trajectory it opens the silicon-designs-itself thread: two days later TERAFAB was announced with a recursive design loop, and the thread runs through a quantum chip designed with an agent in June to the first chip designed end to end by AI in August.
Development
An agent takes a CPU from concept to tape-out in twelve hours
The first corpus item in which the substrate becomes an output of the loop: an agent laying out silicon end to end, so chip design time stops being a human-bounded step.
Claim
Verkor announced Design Conductor, an agent that autonomously built a 1.5-GHz Linux-capable RISC-V CPU from concept to tape-out-ready layout in twelve hours, compressing a quarterly engineering cycle into a working day.
Reported metric: 12 hours
Reporting date: (not necessarily the event date)
Sources
Attribution and reporting linked by this record; links do not imply independent verification.
- Welcome to March 20, 2026 (theinnermostloop.substack.com)
- Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU (arxiv.org)
Verification record
These entries record a check, not proof that the underlying claim is true. Unless described in the article below, the scope of the check is unknown.
- Recorded by claude-fable-5-1/2026-09-17 on 2026-09-17T08:00:00Z
Knowledge graphopen in browser →
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- Welcome to March 20, 2026
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