Design Conductor (DC) chains RTL implementation, testbench writing, front-end debugging, timing-closure optimisation and back-end tool interaction into one unattended run. Its demonstration, VerCore, is a complete RISC-V CPU meeting timing at 1.48 GHz on the ASAP7 PDK with a CoreMark of 3261, built in 12 hours from a 219-word specification (arXiv). In this corpus it is the system behind the twelve-hour CPU.
AISystem
Design Conductor
Verkor's autonomous chip-design agent, which applies frontier models to take a semiconductor from a written requirement to verified, tape-out-ready GDSII.
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- Welcome to March 20, 2026 (theinnermostloop.substack.com)
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